In order to increase the performance of communication processors, hardware accelerators such as offload networks may be typically used. Offload networks are capable of processing data that otherwise would be processed in a processing unit in the communication processor thereby reducing the performance of the processing unit. Offload networks have typically a layered architecture, i.e. a series of network elements may be instantiated between different modules in the communication processor (e.g. IP blocks communicating with the processing unit in the communication processor) to create an offload network that can operate at high speed. The layered architecture may be a modular layered architecture which provides a considerable flexibility of re-using the offload layered network for different applications. Thus, the layered offload network may be used in general purpose communication processors or may be customized for a particular application. The network elements of the series of network elements in successive layers collect trace messages from remote sources and provide synchronization, arbitration and storage of the trace messages. The series of network elements forms a chain of network elements to aggregate data offloaded from the processing unit in the communication processor. Once that data is offloaded from the processing unit in the communication processor, the offloaded data is received from a first set of network elements at a first layer of the layered offload network. Once the offloaded data is processed by the network elements at the first layer, the processed offloaded data is received by a second set of network elements at a second layer and so on until a final network element at a last layer of the layered offload network aggregates all processed offloaded data through the layers of the layered offload network and provides an output of the layered offload network. A number of network elements at the first layer may be greater than a number of network elements at the second layer and the number of network elements at the second layer may be greater than a number of network elements at the third layer until a single network element at the last layer is reached. The network elements of the layered offload network may also provide conversion of the offloaded processed data into various bus formats to allow the output of the layered offload network to access an external memory. The layered offload network may thus provide an alternative path for the communication processor in which the data is not sent directly from the processing unit of the communication processor to the external memory but it is offloaded from the layered offload network and sent to the external memory via the output of the layered offload network.
One of the problems associated with existing layered offload networks is that the increase of performance of the communication processor comes at the expenses of substantial extra power consumption. In fact, in order to offload data from the processing unit in the communication processor, the layered offload network needs to be fully powered-on to ensure offloading of the data and thereby releasing the processing unit from the burden of processing a larger amount of data. In fact the network elements of existing layered offload networks are typically connected to a master power down which turns on or turns off all network elements in the layered offload network. If the layered offload network is designed to work at high clock speeds as it may be usually required, the power consumption of the fully turned on layered offload network during offloading of the data may exceed the maximum power consumption allowed in the particular application for which the layered offload network may be customized.